-- Clk Module


library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity clk is
	port
	(
		clk50Mhz : in std_logic;	-- 20 nS
		reset		: in std_logic;
		clk227Mhz : out std_logic	--2.27 Mhz
	);
end clk;


ARCHITECTURE design of clk is

SIGNAL counter : std_logic_vector(9 downto 0);
SIGNAL clk_out : std_logic;

BEGIN

	PROCESS (clk50Mhz, reset)
	BEGIN
	
	if( reset = '1' ) then
		-- Buttons are pulled down by default
		counter <= (OTHERS => '0');
		clk_out <= '0';
	elsif( clk50Mhz'event and clk50Mhz = '1' ) then
		--if (counter < "1010") then
		if( counter < "1111111111" ) then
			counter <= counter + "1";
		else
			counter <= (OTHERS => '0');
			clk_out <= not clk_out;
		end if;
	end if;

	END PROCESS;


clk227Mhz <= clk_out;	-- ~8.877 Khz


END design;